Physical Design Engineer

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APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Contribute to all phases of the physical design of high-performance PHY design from RTL to delivery of final GDSII. Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines.

Perform block level place and route and close the design to meet timing, area and power constraints. Generate and implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines for other designers to fix LVS/DRC violations. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Master's degree or foreign equivalent in Electrical Engineering or related field.

Experience and/or education must include

• Identifying root-cause LVS DRC ERC issues and closing PDV in order to avoid manufacture and silicon reliability issues.
• Utilizing Tcl, Perl, Python scripting for physical design data mining and flow customization.
• Collecting PPA (power/performance/area) data, demonstrating the tradeoff between power and performance, and coming up with optimal solution for specific design.
• Utilizing low power techniques such as clock gating, power gating to save leakage and dynamic power.
• Utilizing EMIR analysis to understand hot spot violations and fixes.
• Utilizing ML algorithms and models for data mining and improving the design quality and performance.
• Design, simulation, and layout generation using industry standard tools such as Cadence or Virtuoso.
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