Physical Design Engineer

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APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) while meeting schedule and design goals. Perform timing, physical, and electrical verification, and driving the sign off closure for the partitions.

Resolve and improve design and flow issues related to physical design, identifying potential solutions, and driving execution. Explore and implement low power techniques to improve power density for the partitions. Optimize designs for area to achieve a low area footprint for the partitions. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role.

The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Master's degree or foreign equivalent in Electrical and Computer Engineering or related field and 1 year of experience in the job offered or related occupation.

Experience and/or education must include

• Understanding of VLSI design in the context of large chips.
• Knowledge of CMOS fundamentals for logic design.
• Familiarity with Place and Route methodologies (PnR) to implement a design from netlist to GDS.
• Understanding of Static Timing Analysis (STA) concepts to enable timing closure of the placed and routed design.
• Understanding of Physical Design Verification concepts like DRC, LVS and Antenna to enable design fabrication.
• Using Verilog coding to run synthesis experiments to improve PPA, implement ECOs, and debug LVS issues.
• Use of standard cells and compiled memories and their properties to improve quality of designs.
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