Design Verification Engineer

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APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work closely with architecture and RTL designers verifying the functionality correctness of the design. Develop and lead test plans and test environments. Develop complex tests in assembly, C, or vectors according to test plans. Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered. Develop checkers or C-based transactor to verify the design.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related field.

Experience and/or education must include

• Understanding of CPU architecture and system-level behavior to architect robust, high-quality verification strategies.
• Applying root-cause failure analysis, waveform and log debugging, and driving targeted RTL or testbench fixes.
• Utilizing testbench development, including creation of transactors, bus functional models (BFMs), and protocol agents to verify designs comprehensively.
• Designing and deploying architectural and micro-architectural checkers to detect corner cases
• Ownership of coverage-driven verification (CDV), including functional, assertion, and cross-coverage analysis to sign off verification completeness.
• Applying advanced validation techniques such as formal property verification, hardware emulation, and FPGA/SoC bring-up flows to find corner case bugs
• Using industry-standard verification languages and simulation/emulation tools such as C++, System Verilog, Python or Verdi.
• Knowledge of security vulnerabilities like Spectre or Meltdown impacting the modern processors
• Developing directed and constrained-random stimulus to stress pipeline, predictors, ALUs, register files, hazard units, crossbar and performance scenarios.
• Understanding the RTL of modern predictors in CPU like TAGE branch predictors, developing the golden model and verifying the design.
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