Drive the long-term technical goal and architecture for Google’s next-generation TPU firmware, solving complex system-level issues across Security, Power Management, and Telemetry. Act as a technical multiplier and domain expert, mentoring executive engineers and fostering a culture of engineering, high reliability, and innovation across distributed ASIC-Software teams. Forge partnerships across organizational boundaries, bridging silicon design, software infrastructure, and data center deployment teams to co-engineer end-to-end TPU capabilities.
Define and execute multi-year technical roadmaps for multi-generational chip programs, guiding complex firmware initiatives from initial silicon concept through to global data center deployment. Architect highly reliable, real-time on-chip systems and bare-metal microcontroller solutions that maximize AI accelerator performance and optimize the developer experience for platforms like Trillium and Ironwood.
Job description provided by Google.
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