Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure activities. Participate in test plan and coverage analysis of the block and SoC-level verification. Communicate and work with multi-disciplined and multi-site teams.
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