Lead the development and architectural definition of silicon test requirements, driving strategic alignment across design teams, DFT engineers, and external vendors. Define and direct broad strategies for SoC product NPI, bring-up, verification, characterization, and qualification, resolving complex issues across bench testing, test-coverage optimization, and system-to-ATE correlation. Act as a domain expert in ATE testing, leveraging deep industry experience to establish technical standards, architect scalable test solutions, and mentor engineering teams to drive systemic quality improvements.
Influence and partner strategically with design, DFT, and quality teams to shape next-generation chip architectures, ensuring proactive "design-for-testability" and establishing industry-leading best practices for post-silicon testing. Oversee and optimize the chip production life-cycle, driving continuous improvement initiatives for test program architecture, advanced volume data analytics, test time reduction, yield optimization, and complex Return Merchandise Authorization (RMA) failure analysis.
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