Lead SI/PI analysis for High-Performance Computing (HPC) utilizing 2.5D/3D package technologies to define specifications and optimize chip floorplans, power trees, and netlists. Drive next-generation memory interface development and evaluate high-speed Interface IPs, balancing complex trade-offs across IO PHY, SI/PI, and physical design. Own post-silicon validation and qualification of high-speed interfaces to ensure successful New Product Introduction (NPI).
Partner with chip/system design teams, suppliers, and vendors to establish SI/PI goals, define design boundaries, and manage DFM trade-offs. Provide crucial feedback on chip floorplans to maximize package/system routability and SI/PI, while developing methodologies to improve simulation accuracy and productivity.
Job description provided by Google.
View the original posting
