Lead CAD methodology engineers to provide support for chip RTL or Design Verification (DV) teams; and also manage and mitigate support issues for tool flows. Partner with chip project teams to influence and standardize methodology across functional areas and geography. Perform or guide technical evaluations of tools for possible deployment. Collaborate with teams across Google to identify and create opportunities for improved chip design across Google. Participate in design reviews and track issue resolution and engage in technical and schedule trade-off discussions.
Job description provided by Google.
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