Senior Full-Custom Silicon Analog Design Engineer, Raxium

Lead end-to-end full-custom analog modules, encompassing analog IP specifications, architectural definition, seamless integration, and extensive transistor-level design and simulation. Participate in full-chip integration and full-custom Pixel Array IP creation, architecting specialized MicroLED drivers for individual pixel diodes and meeting constraints. Drive transistor-level innovations for ultra-low-power and low-voltage operation across custom logic, standard cells, and ultra-low-power Static Random-Access Memory (SRAM) memory blocks, reducing active and standby power dissipation.

Direct physical layout guidance and parasitic optimization. Partner closely with layout designers on critical floorplanning, symmetry, shielding, matching, and electromigration/IR-drop sign-off. Collaborate closely with RTL designers, micro-architecture teams, and mixed-mode simulation groups using advanced modeling (Verilog-AMS, SystemVerilog RNM) to optimize chip performance, while co-leading post-tapeout silicon bench characterization and debug.