Serve as the principal technical authority across Custom Silicon (TPUs, gSOCs, ASICs) and OTS products (Switches, PCIe, CXL, CPUs), evaluating vendor technical capabilities, architectural trade-offs, node roadmaps, and manufacturability. Work with engineering to help conduct rigorous technical evaluations of leading-edge process nodes (sub-2nm, GAA/RibbonFET, backside power delivery) and specialized nodes. Partner with Tier-1 foundries to assess defect densities, DFM/PDK compliance, and process window margins to secure optimal node execution.
Architect and qualify heterogeneous integration paths (CoWoS, InFO, 3D stacking, HBM integration) and sub-tier components (substrates, thermal interface materials), establishing stringent mechanical and thermal readiness gates (e.g., mTV/eTV stress testing).
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