Physical Design Lead, ASIC

Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff. Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure. Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures.

Manage different PNR tools - synopsys fusion compiler, cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk. Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff. Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.