SoC Design Verification Engineer, Google Cloud

Plan digital design block verification by analyzing specifications and identifying critical scenarios with design engineers. Create and enhance constrained-random environments using SystemVerilog and Universal Verification Methodology (UVM), or execute formal verification using SystemVerilog Assertions (SVA) and industry-leading tools. Identify and write all types of coverage measures for corner-cases. Debug test failures alongside design teams to ensure block correctness. Analyze metrics to resolve coverage gaps and drive progress toward tape-out.