Lead the technical design, architecture, and implementation of high-performance test generators and verification frameworks (e.g., using C++, Python, SystemVerilog, or Universal Verification Methodology (UVM). Propose, design and implement software automation that directly addresses bottlenecks in today's ASIC and SoC Electronic Design Automation (EDA) flow, specifically targeting pseudo-random stimuli generation and constraint-solving methodology.
Collaborate directly with the hardware team on projects to prototype and then deploy scalable test generator tools to make a positive impact on Google's chip hardware development process. Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies for advanced verification. Triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, simulation performance, or service operations and quality.
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