Senior Static Timing Engineer

Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs. Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations. Develop timing constraint and verify it for sign-off. Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts. Own and maintain Primetime STA flows.