(Fastwater Staffing) PCIe Characterization Engineer - Palo Alto, CA (On-site)

HIKINEX

(Fastwater Staffing) PCIe Characterization Engineer - Palo Alto, CA (On-site)

CA, US

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(Fastwater Staffing) PCIe Characterization Engineer - Palo Alto, CA (On-site)

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• Location: Palo Alto, CA (On-site)
• Job Type: Contract

Job Overview

We are seeking an experienced PCIe Characterization Engineer to perform post-silicon electrical characterization and validation of high-speed SerDes PHYs. This role involves hands-on laboratory testing, electrical measurement, signal integrity analysis, and debugging of high-speed interfaces across PCIe, Ethernet, UFS, and LPDDR5 technologies.

The ideal candidate has a strong background in post-silicon characterization or high-speed I/O (HSIO) validation, with practical experience using advanced lab equipment and developing Python scripts for test automation.

Key Responsibilities

• Perform post-silicon electrical characterization of high-speed SerDes PHYs and memory interfaces.
• Conduct eye diagram, jitter, bit error rate (BER), and S-parameter measurements.
• Operate high-speed oscilloscopes, bit error rate testers (BERT), vector network analyzers (VNA), and TDR equipment.
• Analyze schematics and PCB layouts to identify signal integrity issues and support electrical debugging.
• Perform hands-on troubleshooting and debug at the probe point to isolate and resolve hardware-level issues.
• Develop and maintain Python scripts for laboratory test automation, data collection, and analysis.
• Analyze characterization results, document findings, and collaborate with cross-functional engineering teams to improve interface performance.
• Support validation activities for high-speed interfaces, including PCIe, Ethernet, UFS, and LPDDR5.

Required Qualifications

• 5+ years of experience in post-silicon characterization, HSIO validation, SerDes validation, or memory electrical validation.
• Hands-on experience characterizing high-speed electrical interfaces in a semiconductor or systems engineering environment.
• Proficiency with high-speed oscilloscopes, BERT, VNA, and/or TDR measurement equipment.
• Practical experience measuring and analyzing eye diagrams, jitter, BER, and S-parameters.
• Ability to read and interpret schematics and PCB layouts for hardware-level debugging.
• Experience with Python scripting for laboratory automation and test data analysis.
• Strong troubleshooting, analytical, and problem-solving skills.
• Ability to work on-site in Palo Alto, California.

Preferred Qualifications

• Experience with PCIe, Ethernet, UFS, LPDDR5, or other high-speed SerDes and memory interfaces.
• Background working with SoCs, GPUs, networking hardware, storage systems, or automotive computing platforms.
• Experience with signal integrity analysis and post-silicon hardware validation.
• Previous experience in semiconductor, silicon design, or systems companies.

Ideal Candidate Profile

Candidates with titles such as PCIe Characterization Engineer, Signal Integrity Engineer, HSIO Validation Engineer, Post-Silicon Validation Engineer, or SerDes Validation Engineer are encouraged to apply.

Candidates currently based in the San Francisco Bay Area are strongly preferred due to the on-site nature of the position.

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