Network Engineer/AI Fabrics Architect, AI Solutions Lab

Location: Santa Clara, CA

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Solutions Architecture team sits within Marvell's Platform organization, which turns advanced silicon into deployable, customer-ready AI and cloud infrastructure. This team — the AI Solutions Lab — owns the validation layer that proves our platforms perform as promised, across compute, networking, and memory fabrics. Without it, Marvell could design great silicon but could never prove, at rack scale, that it performs the way customers expect — and hyperscalers don't buy chips on paper, they buy validated systems.

Day to day, the team runs AI benchmarking experiments that mirror real customer workloads, operates GPU/HPC lab clusters, validates Marvell's Teralynx switching and AI fabrics under production-like conditions, and builds live demos for trade shows — carrying platform programs from concept to production.

What sets this team apart is breadth of ownership: engineers here aren't limited to validating a single switch chip — they work across the full breadth of Marvell's AI platform portfolio, from Teralynx network fabrics to integrated optical platforms like co-packaged optics (CPO) and near-packaged optics (NPO), as well as emerging memory fabric products such as CXL and photonic fabric memory appliances. This cross-domain ownership — networking, optics, and memory, together — is work that's often siloed across separate teams elsewhere, and the results feed directly into customer proof points and executive reviews.

What You Can Expect

Key Responsibilities

• Own Teralynx-based switch configuration, SONiC deployment, and lab fabric design.
• Design, tune, and validate RoCE-based AI fabrics for scale-up and scale-out workloads.
• Architect rail-optimized, leaf-spine, fat-tree, and multi-plane fabric topologies for distributed training and inference clusters.
• Configure and optimize ECN, PFC, UEC, congestion-control behavior, and telemetry pipelines.
• Analyze GPU collective communication patterns (all-reduce, all-gather, broadcast, reduce-scatter) and their impact on east-west traffic and fabric topology design.
• Work closely with hardware architecture and product management teams to validate and demonstrate features that accelerate AI workflows.
• Debug packet loss, traffic hotspots, head-of-line blocking, and queue behavior using counters and fabric telemetry.
• Build and extend network stress-test and fabric validation to support repeatable, automated benchmark runs.
• Work closely with performance and systems teams to correlate network behavior with end-to-end workload outcomes.
• Produce repeatable network configurations, fabric best practices, and validation artifacts for reuse in customer-facing solutions engagements.

What We're Looking For

Required Qualifications