- Location: United States-Illinois-Rolling Meadows
- RELOCATION ASSISTANCE: Relocation assistance may be available
- CLEARANCE REQUIRED FOR START: Yes
- CLEARANCE TYPE: Secret
- TRAVEL: Yes, 10% of the Time
Description
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way.
Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.
We are seeking talented Principal/Sr. Principal FPGA Design engineers with signal processing experience to join our growing team in Rolling Meadows, IL.
The Multidomain Sensing, Targeting, and Survivability Division (MSTS), located in the Northwest Chicago suburbs, develops operational Electronic Warfare (EW) and targeting systems that provide situational awareness, self-protection, and offensive electronic attack capability to platforms across the spectrum from visible light IR to millimeter wave RF. By joining us, you’ll work on projects that help safeguard our nation related to land forces, rotary wing survivability systems, international and U.S. military electronic warfare systems, communications systems, missile warning systems and sensors, infrared counter-measure systems (IRCM), automatic test equipment, modeling and simulation, and situational awareness programs.
As a Principal/Sr. Principal FPGA Design Engineer, you will join our diverse team and be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our digital signal processing products. You will be working with digital subsystem and circuit card designs that utilize the latest FPGA technologies from all major vendors and device families including Xilinx, Intel (Altera), and Microsemi (Actel) and support high speed interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces.
Your expertise in digital signal processing, modeling and simulation, and circuit level design and test are desired for this position.
This position will be full-time and on-site at our Rolling Meadows, IL. location
This position can be filled at the Principal or Sr. Principal FPGA level based on requirements listed below:
Basic Qualifications for Principal FPGA Design Engineer
Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 5+ years of relevant experience or MS in Electrical Engineering, Computer Engineering or similar related discipline and 3+ years of relevant experience or a PhD in Electrical Engineering, Computer Engineering or similar engineering discipline
In-depth knowledge of VHDL and/or Verilog
Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Catapult HLS) with C++
Expertise achieving timing closure on dense FPGA designs
Working knowledge of DSP structures and techniques
Proficient in Python, C or other scripting languages
Extensive experience generating test benches
Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis
Experience with FPGA simulation tools to verify performance of complex RTL blocks
Experience with Xilinx or Intel/Altera FPGA architectures and design tools
Soft skills to include: Adaptive, creative, collaborative, comfortable working independently, enjoys solving difficult problems while communicating with all levels of an organization internally and externally
US Citizen
Must have interim secret clearance prior to starting and once started, must have the ability to obtain and maintain a full secret clearance.
Basic Qualifications for Sr. Principal FPGA Design Engineer
Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 8+ years of relevant experience or MS in Electrical Engineering, Computer Engineering or similar related discipline and 6+ years of relevant experience or a PhD in Electrical Engineering, Computer Engineering or similar engineering discipline with 4+ years of relevant experience.
In-depth knowledge of VHDL and/or Verilog
Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Catapult HLS) with C++
Expertise achieving timing closure on dense FPGA designs
Working knowledge of DSP structures and techniques
Proficient in Python, C or other scripting languages
Extensive experience generating test benches
Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis
Experience with FPGA simulation tools to verify performance of complex RTL blocks
Experience with Xilinx or Intel/Altera FPGA architectures and design tools
US Citizen
Must have interim secret clearance prior to starting and once started, must have the ability to obtain and maintain a full secret clearance.
Preferred Qualifications
- Current or Active Secret/Top Secret with SCI/SAP security clearance
- Extensive experience implementing Digital Signal or Image Processing algorithms on FPGAs
- Extensive experience with high-speed interfaces: Ex. AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet, etc.
- Working knowledge of SDR platforms and architectures
- Extensive experience developing FPGA algorithms for SoC based architectures
Experience developing FPGA/SW interfaces and controls
Experience developing and prototyping in MATLAB/Simulink
Experience debugging down to the hardware level & experience using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA
Debugging tools.
Experience and knowledge developing requirements for FPGA-based products
Experience with Electronic Design Automation (EDA) Tools: Mentor Graphics ModelSim/QuestaSim, Synplify, Xilinx ISE/ Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder.
Experience working with or developing test benches using SystemVerilog and Universal Verification Methodology (UVM)
Familiarity with revision control, documentation, planning, and review systems similar to GIT/SVN/ClearCase, DOORS, Jira/Rally/ClearQuest
Soft skills to include: Adaptive, creative, collaborative, comfortable working independently, enjoys solving difficult problems while communicating with all levels of an organization internally and externally
Primary Level Salary Range: $119,600.00 - $179,400.00
Secondary Level Salary Range: $149,300.00 - $223,900.00
The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.
Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.
Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.
Job description provided by Northrop Grumman.
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