Senior or Staff Design Verification Engineer

Design Verification Lead Reports To: Head of Engineering About Us Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing. About the Role We are seeking an experienced and hands-on Senior or Staff Design Verification Engineer to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated regression flows.

This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues. Key Responsibilities - Lead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies, test scenarios, coverage goals, and signoff criteria. - Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure. - Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications. - Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces. - Perform and support Clock Domain Crossing (CDC) verification for async and sync clock-domain interfaces. - Develop and maintain UVM-based infrastructure and RAL models where applicable. - Develop checkers, scoreboards, reference models, assertions, and functional coverage to provide comprehensive verification of design behavior. - Perform RTL and gate-level simulation, including SDF-annotated GLS, to identify functional, timing, initialization, reset, and connectivity issues. - Develop and optimize regression and GLS flows using Xcelium and VCS. - Analyze functional and code coverage and drive coverage closure by identifying verification gaps and developing targeted tests. - Debug complex RTL, testbench, simulation, and gate-level failures using waveform and log analysis. - Work closely with RTL designers, analog designers, architects, and silicon validation teams to reproduce issues, determine root cause, and drive resolution. - Review specifications and RTL to identify corner cases, interface issues, reset/clocking problems, and potential functional gaps. - Translate silicon validation findings into simulation-based verification scenarios and regression tests. - Provide technical leadership to a team of verification engineers.

Mentor the team in verification methodologies, tools, and coverage improvements. Qualifications This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA. - Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field - 10+ years of experience in digital verification of SoCs with proven ownership of subsystems or full-chip verification. - Solid Understanding of: - Digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration. - Industry-standard protocols including AMBA, I²C, I3C, SPI, JTAG, and OBI. - Strong Expertise in: - Verilog, SystemVerilog, UVM and class-based verification methodologies. - Constrained-random, coverage-driven verification, regression automation, and verification signoff. - SystemVerilog Assertions (SVA), formal verification techniques. - Python, Perl, and UNIX/Linux shell scripting for automation. - Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP. - Strong analytical and problem-solving skills, with the ability to debug complex issues, communicate clearly, mentor engineers, lead technical initiatives, and cross-functional collaboration skills. - Experience with industry-standard EDA tools (Synopsys, Cadence) Preferred Qualifications - Working knowledge of PMIC architectures and power management principles. - Experience with formal verification techniques Compensation & Benefits Anticipated annual base salary for Member of Technical Staff: $160k - $190k - Stock option grant - Comprehensive benefits package including health, dental, vision, and 401(k)