Senior Staff Engineer – RV (EM/IR)

Role Overview

We are looking for an experiencedSenior Staff Engineer –RV(EM/IR)to lead power integrity and reliability signoff activities for advanced-node SoC designs. In this role, you will drive IR drop and electromigration (EM) analysis, define signoff methodologies, and collaborate with cross-functional teams to achieve robust and reliable silicon implementation. The ideal candidate shouldpossessdeepexpertisein power integrity analysis,strongunderstanding of advanced-node challenges, and proven experience in leading signoff closure for complex chip designs.

WhatYou’llDo

• Lead full-chip and block-level IR drop and electromigration (EM) analysis for advanced-node SoC designs
• Drive power integrity signoff closure byidentifying, debugging, and resolving IR/EM violations
• Collaborate with Physical Design, Power, Package, and Foundry teams to optimize power delivery networks
• Define and improve EM/IRmethodologies, automation flows, and signoff strategies
• Perform static and dynamic IR analysis across multiple operating conditions and scenarios
• Analyze power grid robustness, current density, and thermal impacts to ensure design reliability
• Supporttapeoutactivities and ensure high-quality signoff delivery within project timelines

WhatWe’reLooking For

• 10+ years of experience in IR/EM analysis, power integrity, or Physical Design signoff
• Bachelor’s orMaster’sdegree in Electronics, Electrical Engineering, or VLSI-related discipline
• Strong understanding of power integrity concepts including static/dynamic IR drop, EM analysis, and power grid optimization
• Hands-on experience with industry-standard tools such as CadenceVoltus, Ansys RedHawk, or equivalent
• Good understanding of Physical Design flow includingfloorplanning, placement, CTS, routing, and extraction
• Strong scripting skills inTcl, Python, Perl, or Shell for automation and flow development
• Good to Have
• Experience with advanced technology nodes such as 7nm, 5nm, 3nm, or below
• Exposure to package-aware analysis, thermal analysis, and low-power methodologies
• Experience in leading signoff closure for large-scale SoC or high-performance compute designs
• Success in This Role Looks Like
• Achieving robust IR/EM signoff with minimal iterations and successfultapeoutexecution
• Early identification and resolution of power integrity risksimpactingperformance and reliability
• Improved signoff productivity throughmethodologyenhancements and automation initiatives
• Strong technical leadership and collaboration across implementation and signoff teams

Location

Hybrid / On-site – Bengaluru