Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Conduct floor planning, pin assignments, macro placement and evaluation of logic as well as iterating over placement in order to get the optimized placement. Conduct clock tree synthesis, optimization, routing and post-route optimization.

Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Responsible for the setup, hold, transition and all static timing checks and complete Static Timing Analysis (STA). Run Static IR (Voltage drop) analysis and Dynamic IVD (voltage drop) analysis and other power related optimization and sign off. Responsible for formal checking and sign off, full chip timing closure, physical verification and closure, and signoff checklist closure.

Partner with CAD teams to develop new tools and methodologies that improve physical design productivity and efficiency. Evaluate and/or develop PD-centric flows and methodologies to drive improvements in leakage/dynamic power, area and performance (PPA). Work on top-level full chip Place & Route implementation, complex IP-level partitions, block tiling, feed through planning, and pin assignment. Collaborate with partition level designer and cross functional team to conduct best design solution. 40 hours/week.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $216,200 - $324,800/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Bachelor's degree or foreign equivalent in Electronic Engineering, Electrical Engineering, Computer Engineering or related field and 5 years of progressive, post-baccalaureate experience in the job offered or related occupation.

Experience and/or education must include

• Using Cadence Innovus, Synopsys ICC-2 to work on Place and Route of complex digital logic blocks.
• Utilizing Primetime-SI to analyze timing results and generate fixes needed.
• Ability to use Calibre to understand and debug physical verification results including LVS, DRC and antenna checks.
• Understanding of UPF and knowledge of Conformal-LP to verify low power intent.
• Using Voltus, Redhawk to generate EM and IR results to analyze the power-grid integrity. Ability to generate fixes based on violations reported.
• Knowledge of TCL, Python, TCSH to develop automation scripts that improve efficiency.
• Utilizing Innovus CCOPT to analyze and optimize clock-tree to minimize power, improve latency and skew.
• N/A