Drive the physical layout of high-performance package substrates, from initial bump/ball map feasibility and pin-out optimization to final Gerber/GDS release. Design and layout complex 2.5D/3D architectures, including flip-chip BGA (FCBGA), Silicon Interposers (CoWoS). Partner with SoC designers and System board engineers to co-optimize die-to-package and package-to-board interconnects, and work intimately with Signal and Power Integrity teams to optimize trace routing, decoupling capacitor placement, and power plane geometries to meet electrical targets.
Interface with leading foundries and OSATs to evaluate new packaging technologies, establish Design Rule Checks (DRC), and influence future package technology roadmaps, and develop scripts and CAD methodologies to automate tedious layout tasks, improve design quality, and shorten cycle times.
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