SoC and IP Design Engineer, Networking

Define IP and subsystem micro-architecture specifications, including interface protocols, block diagrams, clocking and reset schemes, register maps, and transaction flows. Integrate complex third-party vendor IPs and internal blocks (such as PCIe subsystems), developing custom SystemVerilog RTL wrappers, glue logic, and protocol adapters. Execute RTL quality sign-off and debug across functional and performance simulation, Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Formal Verification, and Unified Power Format (UPF) checks.

Build and enhance design automation, RTL assembly tooling, and AI-assisted hardware engineering workflows to accelerate integration velocity and design quality. Collaborate with architecture, verification, physical design, DFT, firmware, and external IP vendors on synthesis, timing and power (PPA) closure, coverage analysis, and ASIC silicon bring-up.