ASIC Design Verification Manager, TPU Compute

Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments. Define and drive the execution of comprehensive verification strategies for complex compute subsystems, working with cross-functional design, architecture and power teams to achieve architectural compliance and alignment with performance and power goal.

Architect scalable, reusable verification environments and flows, driving the adoption of industry-leading methodologies to improve efficiency across the team. Provide technical leadership and mentorship to junior engineers, drive code reviews, establish verification quality standards, and guide cross-functional efforts for silicon bring-up. Partner with architects and design leads to influence micro-architectural decisions to improve verification throughput and overall quality.