Lead the definition of verification architectures and methodologies for complex ASIC and SoC designs. Drive the overall verification strategy, including test planning, testbench development, and coverage closure metrics. Architect advanced verification environments using SystemVerilog and UVM to ensure maximum test coverage. Define formal verification strategies to mathematically prove design correctness for critical hardware blocks. Establish emulation and post-silicon validation plans to accelerate system-level integration and debugging.
Job description provided by Google.
View the original posting
