Senior Slurm Administrator

• Location: India, Bengaluru
• NVIDIA is looking for an exceptional engineer to grow and thrive alongside our HPC Infrastructure team that designs, evaluates, and optimizes the compute infrastructure powering NVIDIA's next-generation silicon design and AI
• workloads. You'll own Slurm within NVIDIA's VLSI compute environment and provide second-deep coverage across the wider scheduling estate.

What you'll be doing

• In this position, you will own Slurm within NVIDIA's VLSI compute environment and provide second-deep coverage across the wider scheduling estate.
• Administer, configure and tune Slurm clusters - partitions, QOS, accounting, limits, node states and topology - and operate them alongside an existing LSF estate.
• Automate scheduler operations: node onboarding and draining, configuration management, health checks and routine maintenance.
• Build and maintain dashboards and reporting for job throughput, queue wait times and SLA attainment.
• This is a hands-on technical role. You will be in the cluster and the scripts yourself, supporting design engineers during local business hours, and day-to-day operations - queue health and job triage - are a core part of the job rather than a side activity.

What we need to see

• B.E./B.Tech/M.Tech in Computer Science, Electrical Engineering, or equivalent experience.
• 5+ years in compute infrastructure, with hands-on responsibility for batch scheduling.
• Strong practical Slurm experience: configuration, partitions and QOS, accounting via slurmdbd, node management, and troubleshooting real job failures in production.
• Exposure to a second scheduler, LSF preferred, or a clear appetite to pick one up quickly.
• Solid Linux systems administration - filesystems, NFS, networking, process and resource management.
• Working automation skills in Python and shell, and experience with monitoring and dashboarding tools.
• Comfortable carrying a real operational load - you treat production support and escalations as part of the engineering job. Semiconductor/EDA or HPC exposure is a plus, not a requirement.