Design Verification Engineer, Silicon Engineering

Create and improve constrained-random verification environments using SystemVerilog and UVM. Use SystemVerilog Assertions (SVA) and formal tools for formal verification. Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement power-aware test cases, including stress and corner-case scenarios, for robust power integrity.

Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality. Plan the verification of complex digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.