Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

Define microarchitecture and develop high-quality RTL for memory controller frontends, guiding implementation trade-offs across performance, area, power, timing, and configurability for multi-channel and pseudo-channel configurations. Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, owning quality closure (DFI pipe wrappers, clock/reset, PLL references, sideband bridging) and schedule from concept to tapeout.

Collaborate with DV teams to build test plans, improve coverage, and validate design intent (UVM, emulation, ECC/RAS error injection), while tracking JEDEC specs and memory conferences for the latest HBM trends. Lead and support ATE testing, first-silicon lab bring-up, and physical characterization of the HBM PHY and controller across PVT (process, voltage, temperature) corners. Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, methodology, and systematic root-cause debug.