SoC Constraints Design Engineer, Silicon

Collaborate with Architecture/Microarchitecture/ Register-Transfer Level (RTL) design teams to capture timing intent, and drive timing convergence. Lead the development and validation of Synopsys Design Constraints (SDC) for complex System on a Chip (SoC) subsystems and top-level integration from architecture/microarchitecture documents that gets used in static timing analysis as well as physical design implementation.

Understand clocking structures and Clock Domain Crossing (CDC) strategies to ensure robust timing across all functional and test modes. Design constraints validation across multiple corners/modes using Fishtail/Timevision. Work closely with the design team and block owners throughout the project for sign-off timing convergence. Constraints promotion and demotion flow using fishtail, timevision.